We have scripts that use gccmakedep, which fill up the Makefile with dependencies based on the system it was last run on.
How can we make the clean target in the Makefile automatically remove the dependencies that gccmakedep has added to the Makefile?
(I cannot have a command in the clean target that searches itself for the "# DO NOT DELETE" divider, as gccmakedep itself will find that argument and think that's where it should chop...?)
I think you can make gccmakedep -fdepends.mk produce output into a different makefile. Then you can include it, and remove on clean rule.
-include depends.mk
clean:
@rm -f depends.mk
Personally, I use cc -MMD -MP to generate .d depends and include them in the Makefile. It doesn't need any extra tools and you can clean the .d files along with the object files. Here's an example.
This is also a good writeup by Scott McPeak for more portable solutions and explanation.
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