makefile: fail on single make target if variable empty

Joe J

I'm new to building Makefiles and am trying to determine how fail a build target if a variable is empty. I want to be able to pass in the variable as an environment variable or as a make parameter.

Say I have a makefile like this:

VER ?=

step0:
    echo "step0 should work"

step1: 
    echo "step1 should enforce variable"
    ifeq($(VER), "")
    $(error VER is not set)
    endif 
    echo "Success: Value of Ver ${VER}"

step2:
    echo "step2 should work"

I want to be able to run the following test cases:

VER="foo" make step1  
# should result in printing the "Success:" line

OR

export VER=foo
make step1  
# should result in printing the "Success:" line

OR

make step1 VER=foo  
# should result in printing the "Success:" line

OR

make step1  
# should result in printing "VER is not set"

However, when I run make step using any of the above, I always get the VER is not set error.

Simply put, how can I test for a variable in a specific make target and respond with an error message if it's not set? (but other make targets would not care if the variable is set or not)

Beta

A couple of things:

First, you must keep your Make commands and shell commands neatly segregated. This:

ifeq ($(A),$(B))
...
endif

Is Make syntax. You would probably have trouble if you passed that ifeq (...) to the shell. The commands in a makefile recipe are shell commands, to be passed to the shell. To use the Make ifeq conditional in the middle of a rule, do it like this:

step1:
    some command
ifeq ($(A),$(B))
    another command
endif
    yet another command

Note that there are no TABs preceding ifeq and endif; those are not commands to be passed to the shell, they are for consumption by Make.

Second, this:

ifeq(...)

should be this:

ifeq (...)

The space matters (at least in my version of Make).

Third, this:

ifeq ($(VER), "")

should be this:

ifeq ($(VER),)

unless you actually intend that the variable should contain the string ' ""'.

(You could have discovered those last to yourself, playing with ifeq in isolation; always test new tools in isolation.)

After those changes, the makefile works for me. If it doesn't work for you, let me know and we'll hammer it out.

Collected from the Internet

Please contact [email protected] to delete if infringement.

edited at
0

Comments

0 comments
Login to comment

Related

From Dev

Makefile set variable in target

From Dev

Why does this Makefile fail to build make the final target, but all intermediate targets work fine?

From Dev

Target dependencies from variable in Makefile

From Dev

Generate Target in Makefile from a variable

From Dev

What is the variable $(MAKE) in a makefile?

From Dev

How to make a target in make that is itself named 'makefile'?

From Dev

gcc makefile error: make: *** No rule to make target

From Dev

How to make a target in make that is itself named 'makefile'?

From Dev

Makefile says target is empty but it shouldn't be

From Dev

GNU Make - Set MAKEFILE variable from shell command output within a rule/target

From Dev

Makefile says that variable is empty but it's not

From Dev

makefile : applying a single rule to a bunch of target

From Dev

Makefile: No rule to make target. Stop

From Dev

"No rule to make target 'install'"... But Makefile exists

From Dev

make clean results in no target with specific makefile name

From Dev

C++ Makefile error: No rule to make target

From Dev

Make command using default target name 'Makefile'

From Dev

Makefile issue - No rule to make target 'gcc'

From Dev

Make can find specified target, Makefile cannot

From Dev

Makefile: no rule to make target '*.o', needed by '*'. Stop

From Dev

Makefile produces error "No rule to make target"

From Dev

Makefile, Don't know how to make target

From Dev

make clean results in no target with specific makefile name

From Dev

Recursive makefile No rule to make target `all'. Stop

From Dev

Makefile: no rule to make target '*.o', needed by '*'. Stop

From Dev

How to adapt Makefile for make tests target?

From Dev

Put command result in variable within makefile target

From Dev

Why is there no rule to make target needed by another target in my makefile

From Dev

How do you conditionally call a target based on a target variable (Makefile)?

Related Related

  1. 1

    Makefile set variable in target

  2. 2

    Why does this Makefile fail to build make the final target, but all intermediate targets work fine?

  3. 3

    Target dependencies from variable in Makefile

  4. 4

    Generate Target in Makefile from a variable

  5. 5

    What is the variable $(MAKE) in a makefile?

  6. 6

    How to make a target in make that is itself named 'makefile'?

  7. 7

    gcc makefile error: make: *** No rule to make target

  8. 8

    How to make a target in make that is itself named 'makefile'?

  9. 9

    Makefile says target is empty but it shouldn't be

  10. 10

    GNU Make - Set MAKEFILE variable from shell command output within a rule/target

  11. 11

    Makefile says that variable is empty but it's not

  12. 12

    makefile : applying a single rule to a bunch of target

  13. 13

    Makefile: No rule to make target. Stop

  14. 14

    "No rule to make target 'install'"... But Makefile exists

  15. 15

    make clean results in no target with specific makefile name

  16. 16

    C++ Makefile error: No rule to make target

  17. 17

    Make command using default target name 'Makefile'

  18. 18

    Makefile issue - No rule to make target 'gcc'

  19. 19

    Make can find specified target, Makefile cannot

  20. 20

    Makefile: no rule to make target '*.o', needed by '*'. Stop

  21. 21

    Makefile produces error "No rule to make target"

  22. 22

    Makefile, Don't know how to make target

  23. 23

    make clean results in no target with specific makefile name

  24. 24

    Recursive makefile No rule to make target `all'. Stop

  25. 25

    Makefile: no rule to make target '*.o', needed by '*'. Stop

  26. 26

    How to adapt Makefile for make tests target?

  27. 27

    Put command result in variable within makefile target

  28. 28

    Why is there no rule to make target needed by another target in my makefile

  29. 29

    How do you conditionally call a target based on a target variable (Makefile)?

HotTag

Archive