What are the most useful attributes that can be used with passes in Yosys?
Also, I was wondering if you could give me an example to set 'keep_hierarchy' for a specific module (namely "counter") using 'setattr'.
The README File contains a list of the most prominent attributes. (Section "Verilog Attributes and non-standard features".)
Regarding keep_hierarchy and setattr: Consider the following example code.
module test(input A, B, output X, Y);
test_and and_inst (.A(A), .B(B), .O(X));
test_xor xor_inst (.A(A), .B(B), .O(Y));
endmodule
module test_and(input A, B, output O);
assign O = A & B;
endmodule
module test_xor(input A, B, output O);
assign O = A ^ B;
endmodule
Obviously the following would just display a schematic with a $and and a $xor gate:
yosys -p 'prep; flatten; opt -purge; show test' test.v
Now we can prevent flatten from flattening and_inst by setting the keep_hierarchy attribute on the cell:
yosys -p 'prep; setattr -set keep_hierarchy 1 test/and_inst; flatten; opt -purge; show test' test.v
Alternatively we can prevent all instances of test_and to be flattened by simply setting the attribute on the module itself:
yosys -p 'prep; setattr -mod -set keep_hierarchy 1 test_and; flatten; opt -purge; show test' test.v
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