Rule to set a variable in Makefile not working as expected

debugcn Published at Dev

aarelovich

I'm writing a makefile that can compile different projects depending on the rule used. For this I need to set certain variables to set paths and generate the right output files.

This is the section that is currently not working:

bubblesort: OUTPROG = bubblesort
bubblesort: APP_PATH    = $(SRCS)/bubblesort
bubblesort: OBJS    = ../programs/bubblesort/bubblesort.o
bubblesort: $(COMMON_OBJS) $(OBJS)
    @ echo "<-------------------- Making Bubblesort -------------------->"
    @ echo "<-------------------- Linking files -------------------->"
    $(LD) $(COMMON_OBJS) $(OBJS) $(LDFLAGS)
    @ echo "<-------------------- ELF to Binary File -------------------->"
    $(OC) $(OCFLAGS) $(TARGET) $(BINOUT)
    @ echo "<-------------------- Binary to Verilog Conversion -------------------->"
    $(R2V) $(R2VPARAMS) 


# This is the rule to transform any c code to object file via compilation.
%.o : %.c
    @ echo "<-------------------- Compiling C Source Files -------------------->"
    $(CC) $(CFLAGS_APP) $< -o $@

What happens is that the compilation of the c sources to generate the .o is never invoked (the %.o: %.c rule). However this works:

OBJS        = ../programs/bubblesort/bubblesort.o
bubblesort: OUTPROG = bubblesort
bubblesort: APP_PATH    = $(SRCS)/bubblesort
bubblesort: $(COMMON_OBJS) $(OBJS)
    @ echo "<-------------------- Making Bubblesort -------------------->"
    @ echo "<-------------------- Linking files -------------------->"
    $(LD) $(COMMON_OBJS) $(OBJS) $(LDFLAGS)
    @ echo "<-------------------- ELF to Binary File -------------------->"
    $(OC) $(OCFLAGS) $(TARGET) $(BINOUT)
    @ echo "<-------------------- Binary to Verilog Conversion -------------------->"
    $(R2V) $(R2VPARAMS)

My question is simply why? I would appreciate any input.

EDIT:

Also how can I make the prerequisite depend on the rule invoked?

EDIT 2:

Following the advice from Etan Raiser I modified my code to look like this:

bubblesort: OUTPROG = bubblesort
bubblesort: APP_PATH    = $(SRCS)/bubblesort
bubblesort: $(COMMON_OBJS) ../programs/bubblesort/bubblesort.o creation

creation: $^
    @ echo "<-------------------- Making in general -------------------->"
    @ echo "<-------------------- Linking files -------------------->"
    $(LD) $^ $(LDFLAGS)
    @ echo "<-------------------- ELF to Binary File -------------------->"
    $(OC) $(OCFLAGS) $(TARGET) $(BINOUT)
    @ echo "<-------------------- Binary to Verilog Conversion -------------------->"
    $(R2V) $(R2VPARAMS) 
    @ echo "<-------------------- Creating Obj Dump -------------------->"
    $(OD) $(ODFLAGS) $(TARGET) > $(APP_PATH)/$(OUTPROG)_DUMP.txt

Etan Reisner

It is a question of variable expansion time. (See How make Reads a Makefile.)

The target line bubblesort: $(COMMON_OBJS) $(OBJS) is expanded immediately.

The target-specific variable line bubblesort: OBJS = ../programs/bubblesort/bubblesort.o isn't "executed" (actually doing the assignment) until the bubblesort target is being run.

Instead of this (which doesn't work):

bubblesort: OUTPROG = bubblesort
bubblesort: APP_PATH    = $(SRCS)/bubblesort
bubblesort: OBJS    = ../programs/bubblesort/bubblesort.o
bubblesort: $(COMMON_OBJS) $(OBJS)
    @ echo "<-------------------- Making Bubblesort -------------------->"
    @ echo "<-------------------- Linking files -------------------->"
    $(LD) $(COMMON_OBJS) $(OBJS) $(LDFLAGS)
    @ echo "<-------------------- ELF to Binary File -------------------->"
    $(OC) $(OCFLAGS) $(TARGET) $(BINOUT)
    @ echo "<-------------------- Binary to Verilog Conversion -------------------->"
    $(R2V) $(R2VPARAMS)

and which needs the $(OBJ) variable for the $(LD) call.

You can use:

bubblesort: OUTPROG = bubblesort
bubblesort: APP_PATH    = $(SRCS)/bubblesort
bubblesort: $(COMMON_OBJS) ../programs/bubblesort/bubblesort.o
    @ echo "<-------------------- Making Bubblesort -------------------->"
    @ echo "<-------------------- Linking files -------------------->"
    $(LD) $^ $(LDFLAGS)
    @ echo "<-------------------- ELF to Binary File -------------------->"
    $(OC) $(OCFLAGS) $(TARGET) $(BINOUT)
    @ echo "<-------------------- Binary to Verilog Conversion -------------------->"
    $(R2V) $(R2VPARAMS)

Which works and uses the built-in $^ automatic variable for its intended purpose.

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