我有以下代码:
module s(clock, direction, readWrite, LA1, LA2, LA3, LA4, LD1, LD2, LD3, LD4, RA1, RA2, RA3, RA4, RD1, RD2, RD3, RD4);
// parameters
input clock, direction, readWrite;
inout reg [7:0] LD1, LD2, LD3, LD4, RD1, RD2, RD3, RD4;
inout reg [11:0] LA1, LA2, LA3, LA4, RA1, RA2, RA3, RA4;
// code
always @(posedge clock) begin
if(direction==1) begin // left to right
assign RA1 = LA1 | LA2 | LA3 | LA4;
assign RD1 = LD1 | LD2 | LD3 | LD4;
assign { RA2, RA3, RA4 } = RA1;
assign { RD2, RD3, RD4 } = RD1;
end else begin
if(direction==1) begin // right to left
assign LA1 = RA1 | RA2 | RA3 | RA4;
assign LD1 = RD1 | RD2 | RD3 | RD4;
assign { LA2, LA3, LA4 } = LA1;
assign { LD2, LD3, LD4 } = LD1;
end
end
end
endmodule
但是,在第二行,“ inout reg [7:0] LD1,...”声明在VeritakWin 3.84F中引发语法错误。(Veritak允许一起使用“输出寄存器”,因为在程序中给定的代码之后,我有一个类似的代码)。如果删除“ reg”,则会在分配行中收到错误消息。如果删除“ inout”,显然会出现错误。我什至尝试删除“ assign”关键字,并通过将“ =”替换为“ <=”,但仍然存在错误。我究竟做错了什么?(我是Verilog的新手)
inout
端口不能为类型reg
。assign
您用来为inout
端口分配值的类型称为过程连续分配,但是这种类型的端口不允许这样做。您必须改为使用连续分配。在您的代码中:
module s(clock, direction, readWrite, LA1, LA2, LA3, LA4, LD1, LD2, LD3, LD4, RA1, RA2, RA3, RA4, RD1, RD2, RD3, RD4);
// parameters input clock, direction, readWrite;
inout [7:0] LD1, LD2, LD3, LD4, RD1, RD2, RD3, RD4;
inout [11:0] LA1, LA2, LA3, LA4, RA1, RA2, RA3, RA4;
// left to right
assign RA1 = (direction) ? (LA1 | LA2 | LA3 | LA4) : 'bz;
assign RD1 = (direction) ? (LD1 | LD2 | LD3 | LD4) : 'bz;
assign { RA2, RA3, RA4 } = (direction) ? RA1 : 'bz;
assign { RD2, RD3, RD4 } = (direction) ? RD1 : 'bz;
// right to left
assign LA1 = (!direction) ? (RA1 | RA2 | RA3 | RA4) : 'bz;
assign LD1 = (!direction) ? (RD1 | RD2 | RD3 | RD4) : 'bz;
assign { LA2, LA3, LA4 } = (!direction) ? LA1 : 'bz;
assign { LD2, LD3, LD4 } = (!direction) ? LD1 : 'bz;
endmodule
注意,您不能同时读写inout
端口,因此在读取时设置了高阻抗值。
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