Verilog：为什么“ maxcount”不能保持最大值，而是随“ count”变化？

任何帮助将不胜感激！

我编写此模块是为了跟踪用Verilog编写并在LED阵列上运行的游戏的得分（<= 99）。我希望它能够保持最高分。当电流count大于时maxcount，maxcount将等于电流count，否则将保持其值。

问题是，我不知道为什么maxcount每次count更改都会更改其值（当count减少时，它不能保持其值，而是随着而变小count）

有逻辑错误吗？还是我错过了任何Verilog错误？

非常感谢你！

module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2);
    input Clock, Reset;
    input signed [3:0] pt_0, pt_1, pt_2, pt_3;
    output [6:0] hex1, hex0, hex3, hex2;

    wire signed [6:0] count;
    wire signed [6:0] maxcount;
    score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);

    display(count, maxcount, hex1, hex0, hex3, hex2);

endmodule 

module display (count, maxcount, hex1, hex0, hex3, hex2);
    input [6:0] count, maxcount;
    output [6:0] hex1, hex0, hex3, hex2;

    wire [4:0] unit, unit_m;
    wire [4:0] tens, tens_m;

    assign unit = count % 10;
    assign tens = count / 10;

    assign unit_m = count % 10;
    assign tens_m = count / 10;

    seg7 ud (unit, hex0);
    seg7 td (tens, hex1);
    seg7 umd (unit_m, hex2);
    seg7 tmd (tens_m, hex3);


endmodule 

module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);
    input Clock, Reset;
    //input signed [3:0] sum;
    input [3:0] pt_0, pt_1, pt_2, pt_3;
    parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110;
    //input zero, negative, carry, overflow;

    output signed [6:0] count, maxcount;
    reg signed [6:0] count, maxcount;

    ////wire PS;
    //reg NS;

    always @(posedge Clock)
        if (Reset) begin
            count <= 7'b0;
            maxcount <= 7'b0;
        end else begin
            if (count > maxcount) begin
                maxcount <= count;
            end 
            if (pt_0 == neg_two) begin
                if (count < 2) begin
                    count <= 7'b0;
                end else begin
                    count <= count - 2;
                end
            end else begin
                count <= count + pt_0;
                if (count > 7'b100010) begin
                    count <= 7'b0;
                end
            end

            if (pt_1 == neg_two) begin
                if (count < 2) begin
                    count <= 7'b0;
                end else begin
                    count <= count - 2;
                end
            end else begin
                count <= count + pt_1;
                if (count > 7'b100010) begin
                    count <= 7'b0;
                end
            end

            if (pt_2 == neg_two) begin
                if (count < 2) begin
                    count <= 7'b0;
                end else begin
                    count <= count - 2;
                end
            end else begin
                count <= count + pt_2;
                if (count > 7'b100010) begin
                    count <= 7'b0;
                end
            end

            if (pt_3 == neg_two) begin
                if (count < 2) begin
                    count <= 7'b0;
                end else begin
                    count <= count - 2;
                end
            end else begin
                count <= count + pt_3;
                if (count > 7'b100010) begin
                    count <= 7'b0;
                end
            end
        end
endmodule