VHDL-BCD到二进制输入缓冲区-显示结果的问题

我正在使用Vivado 2014.2将BCD的VHDL代码写入可用于计算器或组合锁的二进制输入缓冲区。

我的方法很简单。做x * 10等于x（2 + 8）= x * 2 + x * 8。

x * 2 = 1左移（2 ^ 1 = 2）

x * 8 = 3个左移（2 ^ 3 = 8）

在添加输入之前，将对输出缓冲区（tempC）进行移位和添加。这样做的目的是，从零开始时，输入的第一个数字不会乘以10。

我的代码可以在artix 7 fpga上编译并运行，但是在确保输出缓冲区（tempC）正常工作时遇到了问题。它拒绝输出任何数据，但是我不确定为什么。

我可能将这些值加在一起是错误的，但我不认为那样。也许我转换为错误的数据类型？

任何帮助是极大的赞赏。

-- Engineer: greatgamer34
-- 
-- Create Date: 01/25/2017 04:57:02 PM
-- Design Name: 
-- Module Name: buff - Behavioral


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity buff is
Port ( Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input
       Clock : in STD_LOGIC;
       Reset : in STD_LOGIC;
       Output : out STD_LOGIC_VECTOR (15 downto 0);
       aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output             for current state.
end buff;

architecture Behavioral of buff is
type states is (state0, state1, state2, state3);
signal currentstate, nextstate: states;
signal tempA: STD_LOGIC_VECTOR (15 downto 0);---used to store 'Data' for addition.
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data').
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register.
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's.
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data')
begin
Process(Reset,clock)
Begin
if(Reset = '1') then
    tempC <= "0000000000000000"; --clear tempC
    tempA <= "0000000000000000"; --clear tempA
    currentstate <= state0; -------reset state to 0
elsif(clock'event and clock = '1') then  
     output <= (tempD);--dispaly the output of the buffer
      currentstate<=nextstate;  -- advance states   
end if;

end process;

process(currentstate)
begin
case currentstate is

when state0 =>
   tempA(3 downto 0) <= Data; -- load in 4 bit data intoi 16 bit register
   tempD <= (tempA); --output the input data(used for debugging)
    nextstate <= state1;
    aout <= not "1111110"; -- output on the 7 seg the number 0


when state1 =>
    tempB <= tempC(14 downto 0) & '0';   --left shift tempC(the output     register) save to tempB; this is the x2 multiplication
    tempD <= (tempA); -- output the input data(used for debugging)
    nextstate <= state2; 
    aout <= not "0110000"; -- output on the 7 seg the number 1

when state2 =>
     tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output      register) three times save to tempE; this is the x8 multiplication
    --tempC <=std_logic_vector( unsigned(tempE) + unsigned(tempD));   (TESTING)
     tempC <=std_logic_vector( ('0' & unsigned(tempE(14 downto 0))) + ('0' &   unsigned(tempD(14 downto 0)))); --add the first 15 bits of tempD and tempE(this      is how we multiply by 10)
    tempD <= (tempC); -- output the x10  output register
    nextstate <= state3; 
    aout <= not "1101101" ;  -- output on the 7 seg the number2 

when state3 =>
   -- tempC <= ('0' & tempC(14 downto 0)) + ('0' & tempA(14 downto 0)); (TESTING)
    tempC <= std_logic_vector( ('0' & unsigned(tempC(14 downto 0))) + ('0' & unsigned(tempA(14 downto 0)))); --add the 'Data' to the x10 shifted number.
    tempD <= (tempC);
    nextstate <= state0; 
    aout <= not "1111001"; -- output on the 7 seg the number3
 end case;
 end process;  
end behavioral;